US 11,758,715 B2
System and method for reducing cell area and current leakage in anti-fuse cell array
Meng-Sheng Chang, Hsinchu (TW); Chia-En Huang, Hsinchu (TW); Shao-Yu Chou, Chu Pei (TW); and Yih Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 28, 2022, as Appl. No. 17/876,103.
Application 17/876,103 is a division of application No. 16/786,499, filed on Feb. 10, 2020, granted, now 11,437,386.
Prior Publication US 2022/0367492 A1, Nov. 17, 2022
Int. Cl. H10B 20/20 (2023.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); G11C 17/16 (2006.01); G06F 30/392 (2020.01); H01L 23/525 (2006.01); G11C 17/18 (2006.01)
CPC H10B 20/20 (2023.02) [G06F 30/392 (2020.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); H01L 23/528 (2013.01); H01L 23/5252 (2013.01); H01L 23/53271 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for creating a standard cell layout of an integrated circuit, the method comprising:
placing a first cell in a first cell row comprising a first active region extending in a first direction, the first cell comprising a first continuous polysilicon line over active region edge (“CPODE”), a first polysilicon line associated with a first read word line, a second polysilicon line associated with a second read word line, and a third polysilicon line associated with a first program word line; and
placing a second cell in a second cell row comprising a second active region extending in the first direction, the second cell comprising a second CPODE, a fourth polysilicon line associated with a second program word line, a fifth polysilicon line associated with a third read word line, and a sixth polysilicon line associated with a fourth read word line,
wherein either the first cell or the second cell is shifted by at least one polysilicon line pitch with respect to the second cell or the first cell, respectively.