| CPC H04L 69/12 (2013.01) [G06F 9/5061 (2013.01); G06F 18/23 (2023.01); H04L 49/90 (2013.01); H04L 67/146 (2013.01)] | 18 Claims |
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1. An electronic device including a multicore comprising:
a communication circuit;
a multicore including a plurality of cores, each core being configured to process data; and
a memory storing execution instructions which, when executed, cause one of the plurality of cores to:
while processing data of packets received by the communication circuit, identify a processing amount of the packets and a session identity (ID) of the packets,
based on the processing amount, a location of a second core that processes application data associated with the session ID of the packets, and a location of a third core that processes driver data associated with the session ID of the packets, identify a location of a first core that processes network data of the packets, the location of the first core including information indicating a core number of the first core and a core type of the first core, the core type indicating a categorization of performance, and
based on the processing amount being equal to or greater than a predetermined level, change the location of the second core that processes application data to be identical to the location of the first core that processes network data,
wherein the first core operates in a lower layer than the second core,
wherein the predetermined level is determined according to at least one of the location of the second core, whether an application associated with the packets is running in a foreground or a background, or a learning process related to the packet processing of the application, and
wherein the changing of the location of the second core comprises selecting a core number of a type having at least one of a same performance or higher performance than the core type of the first core.
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