US 11,757,764 B2
Optimized adaptive routing to reduce number of hops
Abdulla M. Bataineh, Vista, CA (US); Edwin L. Froese, Burnaby (CA); and Duncan Roweth, Bristol (GB)
Assigned to Hewlett Packard Enterprise Development LP, Spring, TX (US)
Appl. No. 17/594,649
Filed by Hewlett Packard Enterprise Development LP, Houston, TX (US)
PCT Filed Mar. 23, 2020, PCT No. PCT/US2020/024170
§ 371(c)(1), (2) Date Oct. 25, 2021,
PCT Pub. No. WO2020/236262, PCT Pub. Date Nov. 26, 2020.
Claims priority of provisional application 62/852,289, filed on May 23, 2019.
Claims priority of provisional application 62/852,203, filed on May 23, 2019.
Claims priority of provisional application 62/852,273, filed on May 23, 2019.
Prior Publication US 2022/0182309 A1, Jun. 9, 2022
Int. Cl. H04L 45/28 (2022.01); H04L 45/028 (2022.01); H04L 45/125 (2022.01); H04L 45/00 (2022.01); H04L 45/122 (2022.01); H04L 47/76 (2022.01); H04L 49/15 (2022.01); H04L 49/00 (2022.01); H04L 69/40 (2022.01); H04L 47/10 (2022.01); H04L 49/9005 (2022.01); H04L 47/34 (2022.01); H04L 67/1097 (2022.01); G06F 13/16 (2006.01); H04L 45/021 (2022.01); H04L 47/12 (2022.01); G06F 13/42 (2006.01); H04L 47/2441 (2022.01); H04L 47/30 (2022.01); H04L 47/62 (2022.01); H04L 47/24 (2022.01); H04L 49/90 (2022.01); G06F 13/38 (2006.01); G06F 13/40 (2006.01); H04L 45/745 (2022.01); H04L 47/2483 (2022.01); H04L 47/629 (2022.01); H04L 47/80 (2022.01); H04L 49/101 (2022.01); H04L 45/12 (2022.01); H04L 47/122 (2022.01); G06F 12/1036 (2016.01); G06F 15/173 (2006.01); H04L 43/10 (2022.01); H04L 45/42 (2022.01); H04L 47/11 (2022.01); G06F 12/0862 (2016.01); G06F 12/1045 (2016.01); H04L 47/32 (2022.01); G06F 9/54 (2006.01); G06F 13/14 (2006.01); G06F 9/50 (2006.01); H04L 47/22 (2022.01); H04L 47/52 (2022.01); H04L 47/6275 (2022.01); H04L 45/24 (2022.01); H04L 45/7453 (2022.01); H04L 45/16 (2022.01); H04L 69/22 (2022.01); H04L 47/762 (2022.01); H04L 47/78 (2022.01); H04L 47/20 (2022.01); H04L 49/9047 (2022.01); H04L 1/00 (2006.01); H04L 43/0876 (2022.01); H04L 47/2466 (2022.01); H04L 47/625 (2022.01); H04L 69/28 (2022.01)
CPC H04L 45/28 (2013.01) [G06F 9/505 (2013.01); G06F 9/546 (2013.01); G06F 12/0862 (2013.01); G06F 12/1036 (2013.01); G06F 12/1063 (2013.01); G06F 13/14 (2013.01); G06F 13/16 (2013.01); G06F 13/1642 (2013.01); G06F 13/1673 (2013.01); G06F 13/1689 (2013.01); G06F 13/385 (2013.01); G06F 13/4022 (2013.01); G06F 13/4068 (2013.01); G06F 13/4221 (2013.01); G06F 15/17331 (2013.01); H04L 1/0083 (2013.01); H04L 43/0876 (2013.01); H04L 43/10 (2013.01); H04L 45/021 (2013.01); H04L 45/028 (2013.01); H04L 45/122 (2013.01); H04L 45/123 (2013.01); H04L 45/125 (2013.01); H04L 45/16 (2013.01); H04L 45/20 (2013.01); H04L 45/22 (2013.01); H04L 45/24 (2013.01); H04L 45/38 (2013.01); H04L 45/42 (2013.01); H04L 45/46 (2013.01); H04L 45/566 (2013.01); H04L 45/70 (2013.01); H04L 45/745 (2013.01); H04L 45/7453 (2013.01); H04L 47/11 (2013.01); H04L 47/12 (2013.01); H04L 47/122 (2013.01); H04L 47/18 (2013.01); H04L 47/20 (2013.01); H04L 47/22 (2013.01); H04L 47/24 (2013.01); H04L 47/2441 (2013.01); H04L 47/2466 (2013.01); H04L 47/2483 (2013.01); H04L 47/30 (2013.01); H04L 47/32 (2013.01); H04L 47/323 (2013.01); H04L 47/34 (2013.01); H04L 47/39 (2013.01); H04L 47/52 (2013.01); H04L 47/621 (2013.01); H04L 47/626 (2013.01); H04L 47/629 (2013.01); H04L 47/6235 (2013.01); H04L 47/6275 (2013.01); H04L 47/76 (2013.01); H04L 47/762 (2013.01); H04L 47/781 (2013.01); H04L 47/80 (2013.01); H04L 49/101 (2013.01); H04L 49/15 (2013.01); H04L 49/30 (2013.01); H04L 49/3009 (2013.01); H04L 49/3018 (2013.01); H04L 49/3027 (2013.01); H04L 49/90 (2013.01); H04L 49/9005 (2013.01); H04L 49/9021 (2013.01); H04L 49/9036 (2013.01); H04L 49/9047 (2013.01); H04L 67/1097 (2013.01); H04L 69/22 (2013.01); H04L 69/40 (2013.01); G06F 2212/50 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/3808 (2013.01); H04L 69/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A switch, comprising:
a processor; and
a memory unit coupled to the processor and including instructions that when executed, cause the processor to:
receive a data packet at an edge of a network, wherein the network comprises a plurality of switches;
determine a packet flow for the packet, wherein packets of the packet flow include same values in one or more header fields;
generate a flow channel for the packet flow, wherein the flow channel indicates a set of paths for the packet flow in the network;
select a forwarding port from a set of ports associated with the flow channel based on respective loads on the set of paths, wherein a respective port corresponds to a different path of the set of paths; and
forward the data packet via the selected forwarding port, wherein the selection of the forwarding port facilitates adaptive routing across a subset of the plurality of switches in accordance with the flow channel.