US 11,757,615 B2
Wideband phase-locked loop for delay and jitter tracking
Yi-Chieh Huang, Zhubei (TW); Ying Wei, San Jose, CA (US); Chung-Ru Wu, Taoyuan (TW); Bo-Yu Chen, Taichung (TW); and Haiming Tang, Cupertino, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Nov. 8, 2021, as Appl. No. 17/521,580.
Prior Publication US 2023/0141897 A1, May 11, 2023
Int. Cl. H04L 7/033 (2006.01); H03L 7/099 (2006.01); H03L 7/091 (2006.01)
CPC H04L 7/0338 (2013.01) [H03L 7/091 (2013.01); H03L 7/0998 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
feed-forward clock circuitry to provide a receiver (RX) clock to a sampler circuit and comprising a first plurality of inverters that cause a temperature-induced delay; and
an RX phase-locked loop (PLL) coupled between the feed-forward clock circuitry and the sampler circuit, the RX PLL comprising a second plurality of inverters having a negative delay that matches the temperature-induced delay of the first plurality of inverters.