US 11,757,613 B2
PAM-4 receiver with jitter compensation clock and data recovery
Chik Patrick Yue, Hong Kong (CN); and Li Wang, Hong Kong (CN)
Assigned to The Hong Kong University of Science and Technology, Hong Kong (CN)
Filed by The Hong Kong University of Science and Technology, Hong Kong (CN)
Filed on May 16, 2022, as Appl. No. 17/744,743.
Claims priority of provisional application 63/190,829, filed on May 20, 2021.
Prior Publication US 2022/0385444 A1, Dec. 1, 2022
Int. Cl. H03D 3/18 (2006.01); H03D 3/24 (2006.01); H04L 7/00 (2006.01); H03L 7/081 (2006.01); H03L 7/08 (2006.01); H03L 7/089 (2006.01); H04L 27/06 (2006.01); H04L 43/087 (2022.01); H03L 7/099 (2006.01); H03M 1/46 (2006.01); H03M 7/16 (2006.01)
CPC H04L 7/0037 (2013.01) [H03L 7/081 (2013.01); H03L 7/0807 (2013.01); H03L 7/0891 (2013.01); H03L 7/0995 (2013.01); H04L 7/0087 (2013.01); H04L 27/06 (2013.01); H04L 43/087 (2013.01); H03M 1/46 (2013.01); H03M 7/165 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A four-level pulse amplitude modulation (PAM-4) receiver with jitter compensation clock and data recovery, comprising:
a continuous-time linear equalizer configured to equalize an input data signal;
a wide-band phase-locked loop (WBPLL) configured to lock to a quarter-rate delay-locked clock signal to generate a plurality of sampling clock signals with evenly separated phases, the plurality of sampling clock signals including N data-sampling clock signals with phases separated by 360°/N and N/2 edge-sampling clock signals with phases separated by 360°/(N/2) and interleaving with the N data-sampling clock signals, where N is a positive even integer;
a data decoder configured to decode the equalized data signal with the N data-sampling clock signals to recover a most significant bit (MSB) signal and a least significant bit (LSB) signal;
an edge detector configured to detect edge information of the equalized data signal with the N/2 edge-sampling clock signals to generate an edge information signal;
a retimer circuit configured to synchronize the recovered MSB signal, the recovered LSB signal and the edge information signal;
a delay-locked loop (DLL) configured to: detect a phase skew of the input signal with reference to the sampling clock signals, produce a delay-line control voltage signal based on the detected phase skew, and generate a delay-locked clock signal based on the delay-line control voltage signal; and
a jitter compensation circuit (JCC) configured to: compensate jitter transfer from the input data signal with a complementary delay-line control voltage signal to generate a jitter-compensated recovered clock signal, a jitter-compensated recovered LSB signal and a jitter-compensated recovered MSB signal.