US 11,757,612 B2
Communicating management traffic between baseboard management controllers and network interface controllers
David F. Heinrich, Houston, TX (US); Gennadiy Rozenberg, Houston, TX (US); Scott P. Faasse, Tomball, TX (US); and Melvin K. Benedict, Houston, TX (US)
Assigned to Hewlett Packard Enterprise Development LP, Spring, TX (US)
Filed by HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP, Houston, TX (US)
Filed on Oct. 29, 2021, as Appl. No. 17/452,823.
Prior Publication US 2023/0134197 A1, May 4, 2023
Int. Cl. H04L 29/06 (2006.01); H04L 7/00 (2006.01)
CPC H04L 7/0037 (2013.01) [H04L 7/0012 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method comprising:
providing, by a first port of a bridge, a reference clock signal to a first end of a first interconnect extending between the first port and a first network interface controller, wherein the reference clock signal propagates over the first interconnect to provide, at a second end of the first interconnect, a first delayed reference clock signal at the first network interface controller;
sensing a timing of the first delayed reference clock signal by the bridge;
communicating management traffic between a network interface of a baseboard management controller and the first network interface controller via the first interconnect, wherein the communicating of the management traffic comprises the first port, responsive to the sensing of the timing of the first delayed reference clock signal, synchronizing communication of data with the first end of the first interconnect to the first delayed reference clock signal;
providing, by a second port of the bridge, the reference clock signal to a first end of a second interconnect extending between the second port and a second network interface controller; and
communicating management traffic between the network interface of the baseboard management controller and the second network interface controller via the second interconnect, comprising synchronizing, by the second port, communication of data with the first end of the second interconnect to the first delayed reference clock signal.