US 11,757,462 B2
Analog-to-digital conversion circuit and receiver including same
Hyochul Shin, Seoul (KR); Seungyeob Baek, Yongin-si (KR); Sungno Lee, Hwaseong-si (KR); Heechang Hwang, Seoul (KR); and Michael Choi, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 18, 2022, as Appl. No. 17/675,342.
Claims priority of application No. 10-2021-0048674 (KR), filed on Apr. 14, 2021.
Prior Publication US 2022/0337260 A1, Oct. 20, 2022
Int. Cl. H03M 1/10 (2006.01); H03L 7/081 (2006.01); H04B 1/16 (2006.01); H04L 25/03 (2006.01); H04L 1/00 (2006.01)
CPC H03M 1/1014 (2013.01) [H03L 7/0812 (2013.01); H04B 1/16 (2013.01); H04L 1/0071 (2013.01); H04L 25/03012 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An analog-to-digital conversion circuit comprising:
a first analog-to-digital converter (ADC), a second ADC and a third ADC collectively configured to perform conversion operations according to a time-interleaving technique; and
a timing calibration circuit configured to
calculate correlation values and determine differences between the correlation values using first samples generated by the first ADC, second samples generated by the second ADC, and third samples generated by the third ADC during sampling periods,
control a phase of a clock signal applied to the second ADC in response to a change in absolute value related to the differences generated during the sampling periods, and
shift the phase of the clock signal in a first direction when the change in absolute value decreases, and shift the phase of the clock signal in a second direction opposite to the first direction when the change in absolute value increases.