US 11,757,027 B2
E-D mode 2DEG FET with gate spacer to locally tune VT and improve breakdown
Rahul Ramaswamy, Portland, OR (US); Nidhi Nidhi, Hillsboro, OR (US); Walid M. Hafez, Portland, OR (US); Johann C. Rode, Hillsboro, OR (US); Paul Fischer, Portland, OR (US); Han Wui Then, Portland, OR (US); Marko Radosavljevic, Portland, OR (US); and Sansaptak Dasgupta, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 13, 2018, as Appl. No. 16/218,882.
Prior Publication US 2020/0194575 A1, Jun. 18, 2020
Int. Cl. H01L 29/778 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/06 (2006.01); H01L 21/8236 (2006.01); H01L 21/8252 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01)
CPC H01L 29/778 (2013.01) [H01L 21/8236 (2013.01); H01L 21/8252 (2013.01); H01L 21/823462 (2013.01); H01L 27/0629 (2013.01); H01L 27/0883 (2013.01); H01L 29/66462 (2013.01); H01L 29/66545 (2013.01); H01L 29/78 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A transistor, comprising:
a semiconductor substrate;
a two dimensional electron gas (2DEG) layer over the semiconductor substrate;
a barrier layer over the 2DEG layer;
a polarization layer over the barrier layer, the polarization layer having a bottommost surface;
an insulating layer over the polarization layer;
a gate electrode through the insulating layer and the polarization layer;
a spacer along sidewalls of the gate electrode, the spacer having a bottommost surface at a same level as the bottommost surface of the polarization layer; and
a gate dielectric between the gate electrode and the barrier layer.