US 11,757,026 B2
Nanowire structures having wrap-around contacts
Stephen M. Cea, Hillsboro, OR (US); Cory E. Weber, Hillsboro, OR (US); Patrick H. Keys, Portland, OR (US); Seiyon Kim, Portland, OR (US); Michael G. Haverty, Mountain View, CA (US); and Sadasivan Shankar, Cupertino, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Oct. 16, 2020, as Appl. No. 17/72,992.
Application 17/072,992 is a continuation of application No. 16/592,380, filed on Oct. 3, 2019, granted, now 10,840,366.
Application 16/592,380 is a continuation of application No. 13/995,914, granted, now 10,483,385, previously published as PCT/US2011/067226, filed on Dec. 23, 2011.
Prior Publication US 2021/0036137 A1, Feb. 4, 2021
Int. Cl. H01L 29/775 (2006.01); H01L 29/66 (2006.01); B82Y 10/00 (2011.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/786 (2006.01); H01L 29/78 (2006.01); H01L 29/16 (2006.01); B82Y 40/00 (2011.01)
CPC H01L 29/775 (2013.01) [B82Y 10/00 (2013.01); H01L 29/0673 (2013.01); H01L 29/41791 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01); B82Y 40/00 (2013.01); H01L 29/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising:
a discrete channel region disposed in the nanowire, the channel region having a length and a perimeter orthogonal to the length, wherein the perimeter of the channel region has a first geometry; and
a pair of source and drain regions disposed in the nanowire, on either side of the channel region, each of the source and drain regions comprising a portion having a perimeter orthogonal to the length of the channel region, wherein the perimeters of the portions of the source and drain regions have a second geometry different than the first geometry of the perimeter of the channel region;
a gate electrode stack surrounding and in contact with the entire perimeter of each of the channel regions;
a pair of conductive contacts, a first of the pair of conductive contacts completely surrounding and in contact with the entire perimeter of the source regions, and a second of the pair of conductive contacts completely surrounding and in contact with the entire perimeter of the drain regions, wherein the pair of conductive contacts has an uppermost surface co-planar with an uppermost surface of the gate electrode stack; and
a pair of spacers adjacent the gate electrode stack.