CPC H01L 29/0665 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823481 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01)] | 20 Claims |
1. A method, comprising:
forming a first semiconductor layer;
forming a plurality of second semiconductor layers over the first semiconductor layer;
forming a first dielectric feature and a second dielectric feature, wherein the first semiconductor layer and the plurality of second semiconductor layers are disposed between the first dielectric feature and the second dielectric feature;
forming a first dielectric layer on the first and second dielectric features and surrounding the first semiconductor layer and the plurality of second semiconductor layers, wherein a gap is formed between a first portion of the first dielectric layer disposed on the first and second dielectric features and a second portion of the first dielectric layer surrounding the first semiconductor layer and the plurality of second semiconductor layers;
forming a mask material in the gap;
removing a portion of the mask material, wherein a remaining mask material is substantially level with a top surface of the first semiconductor layer;
removing a portion of the first dielectric layer over the level of the top surface of the first semiconductor layer;
removing the remaining mask material to form openings in a remaining first dielectric layer;
forming a second dielectric layer in the openings; and
forming a gate electrode layer surrounding the plurality of second semiconductor layers.
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