US 11,756,995 B2
Method of forming a semiconductor device structure having an isolation layer to isolate a conductive feature and a gate electrode layer
Lung-Kun Chu, New Taipei (TW); Mao-Lin Huang, Hsinchu (TW); Chung-Wei Hsu, Hsinchu (TW); Jia-Ni Yu, New Taipei (TW); Kuan-Lun Cheng, Hsinchu (TW); Kuo-Cheng Chiang, Hsinchu (TW); and Chih-Hao Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 27, 2021, as Appl. No. 17/459,379.
Prior Publication US 2023/0061676 A1, Mar. 2, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 29/775 (2006.01); H01L 21/8238 (2006.01); H01L 21/822 (2006.01); H01L 27/06 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01)
CPC H01L 29/0665 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823481 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first semiconductor layer;
forming a plurality of second semiconductor layers over the first semiconductor layer;
forming a first dielectric feature and a second dielectric feature, wherein the first semiconductor layer and the plurality of second semiconductor layers are disposed between the first dielectric feature and the second dielectric feature;
forming a first dielectric layer on the first and second dielectric features and surrounding the first semiconductor layer and the plurality of second semiconductor layers, wherein a gap is formed between a first portion of the first dielectric layer disposed on the first and second dielectric features and a second portion of the first dielectric layer surrounding the first semiconductor layer and the plurality of second semiconductor layers;
forming a mask material in the gap;
removing a portion of the mask material, wherein a remaining mask material is substantially level with a top surface of the first semiconductor layer;
removing a portion of the first dielectric layer over the level of the top surface of the first semiconductor layer;
removing the remaining mask material to form openings in a remaining first dielectric layer;
forming a second dielectric layer in the openings; and
forming a gate electrode layer surrounding the plurality of second semiconductor layers.