CPC H01L 27/0794 (2013.01) [H01L 23/5329 (2013.01); H01L 27/016 (2013.01); H01L 27/0682 (2013.01); H01L 28/20 (2013.01); H01L 28/60 (2013.01)] | 20 Claims |
1. A method, comprising:
providing a first dielectric layer;
sequentially forming a first metal layer, a dummy capacitor dielectric layer, and a second metal layer over the first dielectric layer;
using a single mask layer with two patterns to simultaneously recess two portions of the second metal layer so as to define a metal thin film of a resistor and a top metal plate of a capacitor;
forming a first etch stop layer below the bottom metal plate; and
forming a second etch top layer disposed on a portion of the top surface of the top metal plate and on a portion of a top surface of the metal thin film, wherein the first and the second etch stop layers are each configured to buffer a respective etching process, wherein the second etch stop layer comprises a first portion disposed on the top surface of the metal thin film and a second portion disposed on the top surface of the top metal plate, wherein the first portion, metal thin film, the second portion and the top metal plate are formed using a single first etching mask.
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