CPC H01L 27/0207 (2013.01) [G11C 8/18 (2013.01); H01L 23/481 (2013.01); H01L 25/0657 (2013.01); H01L 27/0688 (2013.01)] | 20 Claims |
1. A memory die, comprising:
a first through-silicon via (TSV) comprising a first input port;
a first output port;
a second TSV comprising a second input port and a second output port;
a memory circuit; and
a logic circuit comprising a comparator and a counter, wherein
the first input port is configured to receive a first input value as a memory die address,
the second input port is configured to receive a second input value, and
the logic circuit is configured to compare the first input value to the second input value.
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