US 11,756,951 B2
Layout design methodology for stacked devices
Fong-yuan Chang, Hsinchu (TW); Po-Hsiang Huang, Tainan (TW); Chin-Chou Liu, Hsinchu (TW); Chin-Her Chien, Chung-Li (TW); and Ka Fai Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 10, 2022, as Appl. No. 17/572,296.
Application 17/572,296 is a division of application No. 16/530,631, filed on Aug. 2, 2019, granted, now 11,222,884.
Claims priority of provisional application 62/772,391, filed on Nov. 28, 2018.
Prior Publication US 2022/0130818 A1, Apr. 28, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); G11C 8/18 (2006.01); H01L 23/48 (2006.01)
CPC H01L 27/0207 (2013.01) [G11C 8/18 (2013.01); H01L 23/481 (2013.01); H01L 25/0657 (2013.01); H01L 27/0688 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory die, comprising:
a first through-silicon via (TSV) comprising a first input port;
a first output port;
a second TSV comprising a second input port and a second output port;
a memory circuit; and
a logic circuit comprising a comparator and a counter, wherein
the first input port is configured to receive a first input value as a memory die address,
the second input port is configured to receive a second input value, and
the logic circuit is configured to compare the first input value to the second input value.