US 11,756,931 B2
Chip package structure with molding layer
Wei-Yu Chen, New Taipei (TW); Li-Hsien Huang, Zhubei (TW); An-Jhih Su, Taoyuan (TW); and Hsien-Wei Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Aug. 3, 2020, as Appl. No. 16/983,315.
Application 16/983,315 is a division of application No. 15/801,846, filed on Nov. 2, 2017, granted, now 10,734,357.
Application 15/801,846 is a division of application No. 15/208,764, filed on Jul. 13, 2016, granted, now 9,825,007, issued on Nov. 21, 2017.
Prior Publication US 2020/0365563 A1, Nov. 19, 2020
Int. Cl. H01L 25/065 (2023.01); H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/03 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/3135 (2013.01); H01L 23/49811 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/97 (2013.01); H01L 25/03 (2013.01); H01L 25/50 (2013.01); H01L 21/561 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/24145 (2013.01); H01L 2224/24227 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06582 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chip package structure, comprising:
a first chip, a second chip, and a third chip, wherein the second chip is between the first chip and the third chip, the second chip comprises a substrate, a bonding pad, an interconnection structure, and a passivation layer, the bonding pad is over the substrate, the passivation layer is over the bonding pad and the substrate, and the interconnection structure is over the bonding pad and embedded in the passivation layer;
a first molding layer surrounding the first chip and the second chip, wherein the first molding layer is a single layer structure, wherein a first boundary surface between the passivation layer and the first molding layer extends toward the first chip;
a second molding layer surrounding the third chip and the first molding layer, wherein a first bottom surface of the first molding layer and a second bottom surface of the second molding layer are coplanar;
a fourth chip adjacent to the first chip, wherein the second chip is between the third chip and the fourth chip, a first portion of the first molding layer is between the first chip and the fourth chip, and both the second chip and the third chip extend across the first portion of the first molding layer,
the first chip has a first sidewall, a second sidewall, and a third sidewall, the second sidewall faces the fourth chip and is between the first sidewall and the third sidewall, the first sidewall is opposite to the third sidewall, the second chip is between the first sidewall and the third sidewall, and the first sidewall is closer to the second chip than the third sidewall in a top view of the first chip, the second chip, and the fourth chip; and
a fifth chip over the first chip and the fourth chip and under the third chip, wherein the fifth chip is between the second chip and the third sidewall of the first chip in a top view of the first chip, the second chip, the third chip, the fourth chip, and the fifth chip.