US 11,756,928 B2
Multi-chip packages
Shuo-Mao Chen, New Taipei (TW); Feng-Cheng Hsu, New Taipei (TW); Han-Hsiang Huang, Pingtung County (TW); Hsien-Wen Liu, Hsinchu (TW); Shin-Puu Jeng, Hsinchu (TW); and Hsiao-Wen Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 22, 2022, as Appl. No. 17/726,545.
Application 17/726,545 is a continuation of application No. 17/006,863, filed on Aug. 30, 2020, granted, now 11,342,306.
Application 17/006,863 is a continuation of application No. 15/795,276, filed on Oct. 27, 2017, granted, now 10,763,239, issued on Sep. 1, 2020.
Prior Publication US 2022/0246579 A1, Aug. 4, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 25/16 (2023.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/5383 (2013.01); H01L 25/16 (2013.01); H01L 25/50 (2013.01); H01L 23/3128 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multi-chip package, comprising:
an interposer disposed over a first side of a first redistribution layer structure and comprising, from bottom to top, an interposer substrate, interposer redistribution layers and interposer connectors;
a first encapsulation layer laterally encapsulating the interposer and in physical contact with the interposer connectors of the interposer;
a second redistribution layer structure disposed over and electrically connected to the interposer connectors of the interposer; and
semiconductor chips disposed over and electrically connected to the second redistribution layer structure.