CPC H01L 24/94 (2013.01) [H01L 21/768 (2013.01); H01L 21/7806 (2013.01)] | 20 Claims |
1. A method of fabricating a semiconductor chip, comprising:
forming a bonding material layer on a first wafer substrate;
patterning the bonding material layer to form a first bonding layer having a strength adjustment pattern in a peripheral region;
forming a semiconductor component layer and a first interconnect structure layer on a second wafer substrate, the first interconnect structure layer being located at a first side of the semiconductor component layer;
forming a second bonding layer on the first interconnect structure layer;
bonding the second wafer substrate to the first wafer substrate by contacting the second bonding layer with the first bonding layer, wherein a bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer;
removing the second wafer substrate;
forming a second interconnect structure layer on the semiconductor component layer at a second side of semiconductor component layer, wherein the second interconnect structure layer is electrically connected to the first interconnect structure layer; and
forming a conductor terminal on the second interconnect structure layer, wherein the conductive terminal is positioned in a component region beside the peripheral region.
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