US 11,756,892 B2
Method for forming chip package structure
Shin-Puu Jeng, Hsinchu (TW); Shuo-Mao Chen, New Taipei (TW); Feng-Cheng Hsu, New Taipei (TW); and Po-Yao Lin, Zhudong Township, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Dec. 14, 2020, as Appl. No. 17/121,051.
Application 17/121,051 is a division of application No. 16/406,874, filed on May 8, 2019, granted, now 10,867,925.
Claims priority of provisional application 62/700,396, filed on Jul. 19, 2018.
Prior Publication US 2021/0098379 A1, Apr. 1, 2021
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 25/16 (2023.01)
CPC H01L 23/5385 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/78 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/562 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 25/162 (2013.01); H01L 24/13 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/16227 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a chip package structure, comprising:
bonding a chip structure to an interposer substrate through a first conductive bump, wherein the interposer substrate comprises a core layer and a conductive via structure passing through the core: layer and electrically connected to the chip structure;
forming a first molding layer over the interposer substrate and surrounding the chip structure;
forming a second conductive bump over the interposer substrate, wherein the interposer substrate is between the second conductive bump and the chip structure;
forming a redistribution structure over a carrier substrate, wherein the redistribution structure has a first surface and a second surface opposite to the first surface, and wherein the redistribution structure comprises a dielectric layer and a conductive pad, the dielectric layer covers the conductive pad, and the conductive pad is disposed at the second surface;
bonding the interposer substrate to the first surface through the second conductive bump;
forming a second molding layer over the redistribution structure and surrounding the first molding layer, the interposer substrate, and the chip structure;
removing the carrier substrate;
partially removing the dielectric layer from the second surface of the redistribution structure to expose a sidewall of the conductive pad; and
forming a third conductive bump over the conductive pad.