US 11,756,883 B2
Through via structure and method
Yung-Chi Lin, Su-Lin (TW); Hsin-Yu Chen, Taipei (TW); Lin-Chih Huang, Hsinchu (TW); Tsang-Jiuh Wu, Hsinchu (TW); and Wen-Chih Chiou, Zhunan Township (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 13, 2020, as Appl. No. 16/927,249.
Application 14/828,110 is a division of application No. 13/619,233, filed on Sep. 14, 2012, granted, now 9,112,007, issued on Aug. 18, 2015.
Application 16/927,249 is a continuation of application No. 15/801,681, filed on Nov. 2, 2017, granted, now 10,714,423.
Application 15/801,681 is a continuation of application No. 14/828,110, filed on Aug. 17, 2015, granted, now 9,831,177, issued on Nov. 28, 2017.
Prior Publication US 2020/0343176 A1, Oct. 29, 2020
Int. Cl. H01L 23/528 (2006.01); H01L 27/088 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/532 (2006.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/525 (2006.01)
CPC H01L 23/528 (2013.01) [H01L 21/76898 (2013.01); H01L 23/3114 (2013.01); H01L 23/3171 (2013.01); H01L 23/481 (2013.01); H01L 23/53238 (2013.01); H01L 24/13 (2013.01); H01L 27/088 (2013.01); H01L 23/525 (2013.01); H01L 23/53223 (2013.01); H01L 23/53252 (2013.01); H01L 23/53266 (2013.01); H01L 23/53271 (2013.01); H01L 24/05 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05024 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/13111 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/13091 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, the method comprising:
forming a first dielectric layer over a first side of a substrate;
forming an opening through the first dielectric layer and into the substrate;
simultaneously forming a first conductive line and a second conductive line, wherein an entirety of the first conductive line is over an upper surface of the first dielectric layer, wherein the second conductive line extends along sidewalls and a bottom surface of the opening, the second conductive line extending over the upper surface of the first dielectric layer; and
forming a second dielectric layer over the first dielectric layer, the first conductive line, and the second conductive line, wherein the second dielectric layer extends lower than the upper surface of the first dielectric layer.