US 11,756,882 B2
Semiconductor die with blast shielding
Enis Tuncer, Dallas, TX (US); and Alejandro Hernandez-Luna, Plano, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Dec. 31, 2020, as Appl. No. 17/138,906.
Prior Publication US 2022/0208676 A1, Jun. 30, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/525 (2006.01); H01L 23/528 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 23/48 (2006.01)
CPC H01L 23/5256 (2013.01) [H01L 23/3107 (2013.01); H01L 23/481 (2013.01); H01L 23/4952 (2013.01); H01L 23/49575 (2013.01); H01L 23/5283 (2013.01)] 39 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a metallic pad and leads;
a semiconductor die including a semiconductor substrate attached to the metallic pad, and a conductor including a sacrificial fuse element above the semiconductor substrate, the sacrificial fuse element being electrically coupled between one of the leads and at least one terminal of the semiconductor die; and
a multilayer dielectric between the sacrificial fuse element and the semiconductor substrate, the multilayer dielectric forming one or more planar gaps beneath a profile of the sacrificial fuse element.