US 11,756,878 B2
Self-aligned via structure by selective deposition
Shao-Kuan Lee, Kaohsiung (TW); Hsin-Yen Huang, New Taipei (TW); Cheng-Chin Lee, Taipei (TW); Hai-Ching Chen, Hsinchu (TW); and Shau-Lin Shue, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 5, 2021, as Appl. No. 17/193,595.
Prior Publication US 2022/0285266 A1, Sep. 8, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76804 (2013.01); H01L 21/76829 (2013.01); H01L 21/76877 (2013.01); H01L 23/5283 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device comprising:
supplying a substrate comprising two or more first level conductors separated by a third dielectric material;
depositing a first inhibitor in direct contact with the first level conductors, while leaving a portion of a top surface of the third dielectric material exposed;
depositing a fourth dielectric material in contact with the exposed portion of the top surface of the third dielectric material;
depositing a first dielectric material over a surface of the substrate; and
forming a via coupled to one of the first level conductors.