US 11,756,870 B2
Stacked via structure disposed on a conductive pillar of a semiconductor die
Che-Yu Yeh, New Taipei (TW); Tsung-Shu Lin, New Taipei (TW); Wei-Cheng Wu, Sinchu (TW); Tsung-Yu Chen, Sinchu (TW); Li-Han Hsu, Hsin-Chu (TW); and Chien-Fu Tseng, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 29, 2021, as Appl. No. 17/243,600.
Prior Publication US 2022/0352060 A1, Nov. 3, 2022
Int. Cl. H01L 23/498 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01)
CPC H01L 23/49822 (2013.01) [H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 25/0652 (2013.01); H01L 2224/2101 (2013.01); H01L 2224/214 (2013.01); H01L 2224/2105 (2013.01); H01L 2224/24226 (2013.01); H01L 2924/182 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A stacked via structure, disposed on a conductive pillar of a semiconductor die, the stacked via structure comprising:
a first dielectric layer covering the semiconductor die;
a first conductive via embedded in the first dielectric layer, wherein the first conductive via is electrically and physically connected to the conductive pillar of the semiconductor die;
a first redistribution wiring covering a top surface of the first conductive via and a top surface of the first dielectric layer;
a second dielectric layer covering the first dielectric layer and the first redistribution wiring;
a second conductive via embedded in the second dielectric layer, wherein the second conductive via is landed on and in physical contact with the first redistribution wiring; and
a second redistribution wiring covering a top surface of the second conductive via and a top surface of the second dielectric layer, wherein a first lateral dimension of the first conductive via is greater than a second lateral dimension of the second conductive via.