US 11,756,857 B2
Electronic circuit, power converter, and method for producing an electronic circuit
Thomas Bigl, Herzogenaurach (DE); Alexander Hensler, Gerhardshofen (DE); Stephan Neugebauer, Erlangen (DE); and Stefan Pfefferlein, Heroldsberg (DE)
Assigned to Siemens Aktiengesellschaft, Munich (DE)
Appl. No. 17/617,844
Filed by Siemens Aktiengesellschaft, Munich (DE)
PCT Filed Jun. 5, 2020, PCT No. PCT/EP2020/065627
§ 371(c)(1), (2) Date Dec. 9, 2021,
PCT Pub. No. WO2020/249479, PCT Pub. Date Dec. 17, 2020.
Claims priority of application No. 19179441 (EP), filed on Jun. 11, 2019.
Prior Publication US 2022/0208643 A1, Jun. 30, 2022
Int. Cl. H01L 23/373 (2006.01); H05K 1/11 (2006.01); H01L 21/48 (2006.01); H01L 25/07 (2006.01); H01L 25/00 (2006.01); H05K 1/02 (2006.01); H05K 1/14 (2006.01); H05K 3/34 (2006.01)
CPC H01L 23/3735 (2013.01) [H01L 21/4807 (2013.01); H01L 25/072 (2013.01); H01L 25/50 (2013.01); H05K 1/0204 (2013.01); H05K 1/115 (2013.01); H05K 1/145 (2013.01); H05K 3/341 (2013.01); H05K 2201/068 (2013.01)] 39 Claims
OG exemplary drawing
 
28. A power converter comprising:
two or more electronic circuits; and
a common circuit carrier which forms a corresponding first circuit carrier for each of the two or more electronic circuits;
the first circuit carrier having a first via and a second via, a second circuit carrier, and a third circuit carrier, a power-electronic first semiconductor component having an upper side that lies against an underside of the first circuit carrier and an underside which lies against an upper side of the second circuit carrier, with the first via electrically connecting the upper side of the first semiconductor component to a first conductor path of the first circuit carrier, with the second via electrically connecting a first connection element arranged between the underside of the first circuit carrier and the upper side of the second circuit carrier to a second conductor path of the first circuit carrier, the first connection element forming an integral connection between the upper side of the second circuit carrier and the underside of the first circuit carrier and a second semiconductor component having an upper side that lies against the underside of the first circuit carrier and is electrically connected to the first conductor path or to the second conductor path, and an underside that lies against an upper side of the third circuit carrier; wherein a lateral thermal expansion coefficient of the first circuit carrier is greater than a lateral thermal expansion coefficient of the second circuit carrier and greater than a lateral thermal expansion coefficient of the third circuit carrier, and
wherein the power-electronic first semiconductor component upper side is chip bonded to the underside of the first circuit carrier and the power-electronic first semiconductor component underside is chip bonded with a sintered connection to the upper side of the second circuit carrier at two contacts with one of the two contacts being larger than the other, and the second semiconductor component upper side is chip bonded to the second semiconductor component underside of the first circuit carrier and the second semiconductor component underside is chip bonded with a sintered connection to the upper side of the third circuit carrier at two contacts with one of the two contacts being larger than the other.