US 11,756,848 B1
Chip integration into cavities of a host wafer using lateral dielectric material bonding
Florian Herrault, Agoura Hills, CA (US); Isaac Rivera, Buena Park, CA (US); Daniel S. Green, McLean, VA (US); and James F. Buckwalter, Santa Barbara, CA (US)
Assigned to PseudolithIC, Inc., Santa Barbara, CA (US)
Filed by PseudolithIC, Inc., Santa Barbara, CA (US)
Filed on Jan. 17, 2023, as Appl. No. 18/155,607.
Int. Cl. H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/3114 (2013.01) [H01L 21/561 (2013.01); H01L 24/96 (2013.01); H01L 2224/96 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method of assembling an electronic assembly comprising:
bonding a front surface of a wafer having the front surface, a back surface, and cavities having side surfaces of the wafer to a top surface of an adhesive laminate having the top surface and a bottom surface such that the cavities are disposed over a plurality of areas of the top surface of the adhesive laminate;
bonding a frontside of a plurality of chiplets having a backside and the frontside to a portion of the plurality of areas of the top surface of the adhesive laminate; and
molding a lateral dielectric material between side surfaces of the chiplets and the side surfaces of the cavities, the lateral dielectric material bonding the side surfaces of the chiplets to the side surfaces of the cavities; and
forming direct interconnects of conductive material from the chiplets, directly on the lateral dielectric material, and to wafer electrical routing of the wafer.