CPC H01L 22/34 (2013.01) [H01L 21/78 (2013.01); H01L 22/32 (2013.01)] | 7 Claims |
1. A semiconductor device comprising:
a substrate including a chip region, a first scribe lane, and a second scribe lane, the first scribe lane on a first side of the chip region, the second scribe lane on a second side of the chip region, the first side of the chip region being perpendicular to the second side of the chip region;
a memory cell structure on the chip region of the substrate;
a first insulation layer disposed on the substrate and covering the memory cell structure, the first insulation layer having a first sidewall that is disposed on the first scribe lane of the substrate, and a second sidewall that is disposed between the first sidewall and the first scribe lane of the substrate;
a pattern group on the first scribe lane of the substrate, the pattern group including a first wiring that is disposed in the first insulation layer, and a second wiring that is disposed on the first insulation layer;
a second insulation layer disposed on the first insulation layer and exposing a top surface of the second wiring of the pattern group; and
a third wiring on the second insulation layer,
wherein the first wiring and the second wiring of the pattern group are in electrical contact with each other,
the third wiring is spaced apart from the second wiring of the pattern group,
a thickness of the third wiring in a direction that is perpendicular to a top surface of the substrate is greater than a thickness of at least one of the first wiring, or the second wiring of the pattern group in the direction, and
surface roughness of the first sidewall of the first insulation layer differs from surface roughness of a sidewall of the first scribe lane of the substrate.
|