US 11,756,823 B2
Method for manufacturing body-source-tied SOI transistor
Allan K Calvo, Tustin, CA (US); Paul D Hurwitz, Irvine, CA (US); and Roda Kanawati, Irvine, CA (US)
Assigned to Newport Fab, LLC, Newport Beach, CA (US)
Filed by Newport Fab, LLC, Newport Beach, CA (US)
Filed on Jul. 13, 2022, as Appl. No. 17/863,925.
Application 17/863,925 is a division of application No. 16/928,962, filed on Jul. 14, 2020, granted, now 11,581,215.
Prior Publication US 2022/0352007 A1, Nov. 3, 2022
Int. Cl. H01L 27/12 (2006.01); H01L 21/762 (2006.01); H01L 29/49 (2006.01); H01L 23/66 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01)
CPC H01L 21/76243 (2013.01) [H01L 23/66 (2013.01); H01L 27/1203 (2013.01); H01L 29/1087 (2013.01); H01L 29/4238 (2013.01); H01L 29/4916 (2013.01); H01L 29/7833 (2013.01); H01L 29/665 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor-on-insulator (SOI) transistor comprising:
providing a semiconductor layer situated over a buried oxide layer, said buried oxide layer being situated over a substrate;
forming a transistor body having a first conductivity type in said semiconductor layer;
forming gate fingers over said transistor body;
forming source regions and drain regions having a second conductivity type opposite to said first conductivity type;
forming a heavily-doped body-implant region having said first conductivity type overlapping at least one of said source regions;
forming a common silicided region electrically tying said heavily-doped body-implant region to said at least one of said source regions;
wherein said heavily-doped body-implant region is situated partially outside said source regions and near gate contacts;
wherein at least one of said gate fingers comprises a stub adjacent to said heavily-doped body-implant region.