CPC H01L 21/76243 (2013.01) [H01L 23/66 (2013.01); H01L 27/1203 (2013.01); H01L 29/1087 (2013.01); H01L 29/4238 (2013.01); H01L 29/4916 (2013.01); H01L 29/7833 (2013.01); H01L 29/665 (2013.01)] | 20 Claims |
1. A method of manufacturing a semiconductor-on-insulator (SOI) transistor comprising:
providing a semiconductor layer situated over a buried oxide layer, said buried oxide layer being situated over a substrate;
forming a transistor body having a first conductivity type in said semiconductor layer;
forming gate fingers over said transistor body;
forming source regions and drain regions having a second conductivity type opposite to said first conductivity type;
forming a heavily-doped body-implant region having said first conductivity type overlapping at least one of said source regions;
forming a common silicided region electrically tying said heavily-doped body-implant region to said at least one of said source regions;
wherein said heavily-doped body-implant region is situated partially outside said source regions and near gate contacts;
wherein at least one of said gate fingers comprises a stub adjacent to said heavily-doped body-implant region.
|