US 11,756,647 B2
Memory device and electronic device
Chien-Yu Huang, Hsinchu (TW); Chia-En Huang, Hsinchu (TW); Cheng Hung Lee, Hsinchu (TW); and Hua-Tai Shieh, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 17, 2022, as Appl. No. 17/843,591.
Application 17/843,591 is a continuation of application No. 17/135,043, filed on Dec. 28, 2020, granted, now 11,367,507.
Application 17/135,043 is a continuation of application No. 16/509,178, filed on Jul. 11, 2019, granted, now 10,878,934, issued on Dec. 29, 2020.
Claims priority of provisional application 62/698,640, filed on Jul. 16, 2018.
Prior Publication US 2022/0319631 A1, Oct. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/00 (2006.01); G06F 11/16 (2006.01); G11C 8/10 (2006.01); G11C 7/12 (2006.01)
CPC G11C 29/702 (2013.01) [G06F 11/1666 (2013.01); G11C 7/12 (2013.01); G11C 8/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
providing a first column of memory cells, wherein a first local redundancy decoder circuit is operably connected to the first column of memory cells;
providing a second column of memory cells immediately adjacent the first column of memory cells, wherein a second local redundancy decoder circuit is operably connected to the second column of memory cells, and wherein the first local redundancy decoder circuit differs from the second local redundancy decoder circuit;
providing a third column of memory cells, wherein a separate first local redundancy decoder circuit is operably connected to the third column of memory cells;
providing a fourth column of memory cells immediately adjacent the third column of memory cells, wherein a separate second local redundancy decoder circuit is operably connected to the fourth column of memory cells;
determining the first column of memory cells is to be repaired;
rippling a first output signal from the separate first local redundancy circuit operably connected to the third column of memory cells to a first input of the second local redundancy circuit operably connected to the second column of memory cells;
rippling a second output signal from the first local redundancy circuit operably connected to the first column of memory cells to a second input of the second local redundancy circuit operably connected to the second column of memory cells; and
using the first output signal received at the first input and the second output signal received at the second input in a decoding operation by the second local redundancy circuit operably connected to the second column of memory cells for repairing the first column of memory cells.