US 11,756,640 B2
MIM efuse memory devices and fabrication method thereof
Meng-Sheng Chang, Chu-bei (TW); Chia-En Huang, Xinfeng Township (TW); and Yih Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 6, 2021, as Appl. No. 17/396,398.
Prior Publication US 2023/0043443 A1, Feb. 9, 2023
Int. Cl. G11C 17/00 (2006.01); G11C 17/16 (2006.01); H10B 20/20 (2023.01)
CPC G11C 17/165 (2013.01) [H10B 20/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of memory cells, each of the memory cells including an access transistor and a resistor coupled to each other in series, wherein each of the memory cells includes a one-time programmable (OTP) electrical fuse;
wherein the resistors of the memory cells are each configured to be programmed from a first resistance state to a second resistance state and are formed as one of a plurality of metal structures disposed over a substrate; and
wherein the access transistors of the memory cells are disposed opposite a first metallization layer containing the plurality of metal structures from the substrate.