CPC G11C 17/165 (2013.01) [H10B 20/20 (2023.02)] | 20 Claims |
1. A memory device, comprising:
a plurality of memory cells, each of the memory cells including an access transistor and a resistor coupled to each other in series, wherein each of the memory cells includes a one-time programmable (OTP) electrical fuse;
wherein the resistors of the memory cells are each configured to be programmed from a first resistance state to a second resistance state and are formed as one of a plurality of metal structures disposed over a substrate; and
wherein the access transistors of the memory cells are disposed opposite a first metallization layer containing the plurality of metal structures from the substrate.
|