CPC G11C 16/0483 (2013.01) [G11C 16/12 (2013.01); G11C 17/165 (2013.01)] | 15 Claims |
1. A memory circuit comprising: a first memory cell including: a first resistor; a first transistor coupled to the first resistor, wherein a first bulk port of the first transistor is biased at a first voltage level; a second memory cell coupled to the first memory cell, the second memory cell including: a second resistor; a second transistor coupled to the second memory cell, wherein a second bulk port of the second transistor is biased at a second voltage level, wherein the second voltage level is less than the first voltage level; and a read access transistor coupled to each of the first memory cell and the second memory cell, wherein, in response to the read access transistor receiving a read bit line voltage, a sensing circuit coupled to the read access transistor senses at least one of the first memory cell or the second memory cell.
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