US 11,756,622 B2
Bank design with differential bulk bias in eFuse array
Meng-Sheng Chang, Chubei (TW); and Chia-En Huang, Xinfeng Township (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Sep. 22, 2021, as Appl. No. 17/448,486.
Claims priority of provisional application 63/175,699, filed on Apr. 16, 2021.
Prior Publication US 2022/0336018 A1, Oct. 20, 2022
Int. Cl. G11C 17/18 (2006.01); G11C 16/04 (2006.01); G11C 17/16 (2006.01); G11C 16/12 (2006.01)
CPC G11C 16/0483 (2013.01) [G11C 16/12 (2013.01); G11C 17/165 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A memory circuit comprising: a first memory cell including: a first resistor; a first transistor coupled to the first resistor, wherein a first bulk port of the first transistor is biased at a first voltage level; a second memory cell coupled to the first memory cell, the second memory cell including: a second resistor; a second transistor coupled to the second memory cell, wherein a second bulk port of the second transistor is biased at a second voltage level, wherein the second voltage level is less than the first voltage level; and a read access transistor coupled to each of the first memory cell and the second memory cell, wherein, in response to the read access transistor receiving a read bit line voltage, a sensing circuit coupled to the read access transistor senses at least one of the first memory cell or the second memory cell.