US 11,756,616 B2
Computer and calculation method using memristor array
Hiroshi Nakao, Yamato (JP); Masayuki Hiromoto, Kawasaki (JP); Hisanao Akima, Kawasaki (JP); Teruo Ishihara, Sagamihara (JP); and Takuji Yamamoto, Hachiouji (JP)
Assigned to FUJITSU LIMITED, Kawasaki (JP)
Filed by FUJITSU LIMITED, Kawasaki (JP)
Filed on Nov. 10, 2021, as Appl. No. 17/522,959.
Claims priority of application No. 2021-025552 (JP), filed on Feb. 19, 2021.
Prior Publication US 2022/0270683 A1, Aug. 25, 2022
Int. Cl. G11C 7/02 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/0069 (2013.01) [G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0038 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A computer comprising:
a memristor array including memristors, the memristors being arranged at intersections between a plurality of word lines and a first bit line in the memristor array and being arranged at intersections between the plurality of word lines and a plurality of second bit lines in the memristor array;
an adder circuit configured to obtain sum voltages for the plurality of second bit lines by adding a plurality of first voltages to difference voltages, the plurality of first voltages being voltages generated according to currents that flow in the plurality of second bit lines when a first pattern is supplied to the plurality of word lines, the difference voltages being voltages between a reference voltage generated according to a current that flows in the first bit line when a second pattern is supplied to the plurality of word lines and a plurality of second voltages generated according to currents that flow in the plurality of second bit lines when a second pattern is supplied to the plurality of word lines; and
a detection circuit configured to detect a second bit line that corresponds to a maximum value of the sum voltages.