CPC G11C 13/0069 (2013.01) [G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0038 (2013.01)] | 9 Claims |
1. A computer comprising:
a memristor array including memristors, the memristors being arranged at intersections between a plurality of word lines and a first bit line in the memristor array and being arranged at intersections between the plurality of word lines and a plurality of second bit lines in the memristor array;
an adder circuit configured to obtain sum voltages for the plurality of second bit lines by adding a plurality of first voltages to difference voltages, the plurality of first voltages being voltages generated according to currents that flow in the plurality of second bit lines when a first pattern is supplied to the plurality of word lines, the difference voltages being voltages between a reference voltage generated according to a current that flows in the first bit line when a second pattern is supplied to the plurality of word lines and a plurality of second voltages generated according to currents that flow in the plurality of second bit lines when a second pattern is supplied to the plurality of word lines; and
a detection circuit configured to detect a second bit line that corresponds to a maximum value of the sum voltages.
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