US 11,756,611 B2
Memory system
Tokumasa Hara, Kawasaki (JP); and Noboru Shibata, Kawasaki (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jan. 24, 2022, as Appl. No. 17/582,330.
Application 17/582,330 is a continuation of application No. 17/014,293, filed on Sep. 8, 2020, granted, now 11,264,090.
Claims priority of application No. 2019-166519 (JP), filed on Sep. 12, 2019; and application No. 2020-104833 (JP), filed on Jun. 17, 2020.
Prior Publication US 2022/0148651 A1, May 12, 2022
Int. Cl. G11C 11/00 (2006.01); G11C 11/56 (2006.01); G06F 3/06 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); H10B 69/00 (2023.01)
CPC G11C 11/56 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/0483 (2013.01); H10B 69/00 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A memory system comprising:
a nonvolatile memory including a plurality of memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region indicating an erased state for erasing data and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region and indicating a written state for writing data; and
a controller configured to send a first command to the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then send a second command to the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit, wherein
among fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit, and the number of fourth boundaries used for determining a value of the data of the fourth bit are 1, 4, 5, 5 or 4, 1, 5, 5 in order,
the controller is configured to send the first command to the nonvolatile memory to execute the first program such that the threshold region in the memory cell is any threshold region of a seventeenth threshold region indicating an erased state for erasing data and eighteenth to twentieth threshold regions having higher voltage levels than a voltage level of the seventeenth threshold region and indicating a written state for writing data according to the data of the first bit and the second bit,
the n-th threshold region has a higher voltage level than the (n−1)-th threshold region (n is a natural number of two or more and sixteen or less),
the k-th threshold region has a higher voltage level than the (k−1)-th threshold region (k is a natural number of eighteen or more and twenty or less),
the controller is configured to send the second command to the nonvolatile memory to execute the second program such that the threshold region in the memory cell is any threshold region of four threshold regions among the first to sixteenth threshold regions from any threshold region of the seventeenth to twentieth threshold regions according to the data of the third bit and the fourth bit, and
the number of threshold regions between a threshold region having a lowest voltage level and a threshold region having a highest voltage level among the four threshold regions is four or less.