US 11,756,603 B2
Memory-element-including semiconductor device
Nozomu Harada, Tokyo (JP); and Koji Sakui, Tokyo (JP)
Assigned to UNISANTIS ELECTRONICS SINGAPORE PTE. LTD., Singapore (SG)
Filed by Unisantis Electronics Singapore Pte. Ltd., Singapore (SG)
Filed on Apr. 11, 2022, as Appl. No. 17/717,779.
Claims priority of application No. PCT/JP2021/015527 (WO), filed on Apr. 15, 2021.
Prior Publication US 2022/0336002 A1, Oct. 20, 2022
Int. Cl. G11C 11/402 (2006.01); G11C 11/4097 (2006.01); G11C 5/10 (2006.01)
CPC G11C 11/4023 (2013.01) [G11C 5/10 (2013.01); G11C 11/4097 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A memory-element-including semiconductor device comprising:
a dynamic flash memory region in which, on a substrate, a plurality of dynamic flash memory cells are arranged in a two-dimensional array, and a signal processing-driving circuit region disposed outside of the dynamic flash memory region and including a plurality of transistors configured to perform signal processing-driving of the plurality of dynamic flash memory cells,
wherein each of the dynamic flash memory cells included in the dynamic flash memory region includes
a semiconductor pillar standing on the substrate in a direction perpendicular to the substrate,
a first impurity layer connecting to a bottom portion of the semiconductor pillar,
a second impurity layer connecting to a top portion of the semiconductor pillar,
a first gate insulating layer surrounding a lower portion of the semiconductor pillar and being in contact with the first impurity layer,
a second gate insulating layer being in contact with the first gate insulating layer, surrounding an upper portion of the semiconductor pillar, and being in contact with the second impurity layer,
a first gate conductor layer covering a portion of or an entirety of the first gate insulating layer,
a second gate conductor layer covering the second gate insulating layer, and
a first insulating layer disposed between the first gate conductor layer and the second gate conductor layer, and
is configured to control voltages applied to the first impurity layer, the second impurity layer, the first gate conductor layer, and the second gate conductor layer to perform a memory write operation, a memory erase operation, and a memory read operation, and
the memory-element-including semiconductor device further comprises a first wiring conductor layer disposed, in plan view, in the dynamic flash memory region, connecting to the second impurity layer of each dynamic flash memory cell, extending parallel to the substrate, and having an upper-surface position, in the perpendicular direction, lower than an uppermost semiconductor layer of the signal processing-driving circuit region, and
a high-thermal-conductivity material layer positioned higher than the first wiring conductor layer.