| CPC G11C 7/222 (2013.01) [G11C 7/1012 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 7/20 (2013.01); G11C 8/18 (2013.01)] | 20 Claims |
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1. An operation method of a storage device which includes a storage controller circuit and a nonvolatile memory device, the method comprising:
performing a first boot-up operation;
performing first training on a plurality of data signals such that a detection operation of the first training is repeatedly performed on windows of the data signals;
storing offset information generated based on a result of the first training;
performing a normal operation based on the result of the first training;
performing a second boot-up operation;
performing second training on the plurality of data signals based on the offset information generated in the first training such that a detection operation of the second training is repeatedly performed on a left edge section and a right edge section of the windows of the data signals; and
performing the normal operation based on a result of the second training,
wherein the detection operation of the first training includes:
sending, by the storage controller circuit, a read command and an address to the nonvolatile memory device through the plurality of data signals;
receiving, by the storage controller circuit, pattern data from the nonvolatile memory device through the plurality of data signals and a data strobe signal synchronized with the plurality of data signals; and
when the pattern data are not matched with given reference data, adjusting, by the storage controller circuit, a delay amount of the data strobe signal.
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