US 11,756,591 B2
Switches to reduce routing rails of memory system
Meng-Sheng Chang, Chu-bei (TW); Chia-En Huang, Xinfeng Township (TW); Yi-Ching Liu, Hsinchu (TW); and Yih Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 28, 2021, as Appl. No. 17/460,215.
Prior Publication US 2023/0066081 A1, Mar. 2, 2023
Int. Cl. G11C 5/06 (2006.01)
CPC G11C 5/063 (2013.01) 17 Claims
OG exemplary drawing
 
1. A memory array comprising:
a first set of memory cells including:
a first subset of memory cells connected between a first local bit line and a first local select line extending along a first direction, and
a second subset of memory cells connected between a second local bit line and a second local select line extending along the first direction;
a first switch connected between the first local bit line and a first global bit line, wherein the first global bit line extends along a second direction; and
a second switch connected between the second local bit line and the first global bit line,
wherein a gate electrode of the first switch is electrically coupled to a first switch control line extending along a third direction, and
wherein a gate electrode of the second switch is electrically coupled to a second switch control line extending along the third direction,
wherein each memory cell of the first subset of memory cells includes a gate electrode connected to a gate electrode of a corresponding memory cell of the second subset of memory cells through a respective local word line extending along the second direction.