US 11,756,289 B2
Information processing apparatus, arithmetic processing device, and method of controlling information processing apparatus
Ryo Takata, Kawasaki (JP); and Masanori Higeta, Setagaya (JP)
Assigned to FUJITSU LIMITED, Kawasaki (JP)
Filed by FUJITSU LIMITED, Kawasaki (JP)
Filed on Jan. 15, 2020, as Appl. No. 16/742,948.
Claims priority of application No. 2019-021938 (JP), filed on Feb. 8, 2019.
Prior Publication US 2020/0257498 A1, Aug. 13, 2020
Int. Cl. G06F 7/48 (2006.01); G06V 10/82 (2022.01); G06N 3/02 (2006.01); G06N 5/04 (2023.01); G10L 25/51 (2013.01); G06F 18/25 (2023.01); G06V 10/764 (2022.01)
CPC G06V 10/82 (2022.01) [G06F 7/48 (2013.01); G06F 18/253 (2023.01); G06N 3/02 (2013.01); G06N 5/04 (2013.01); G06V 10/764 (2022.01); G10L 25/51 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An information processing apparatus comprising:
a first preprocessing arithmetic device configured to execute preprocessing for first analog data from a first sensor; and
a first post-processing arithmetic device connected to the first preprocessing arithmetic device and configured to execute post-processing for first preprocessed data output by the first preprocessing arithmetic device,
the first preprocessing arithmetic device includes a first processor configured to:
receive the first analog data from the first sensor and convert the first analog data into digital data;
output feature data on the basis of a result of execution of feature extraction processing for the digital data; and
output the feature data, and
the first post-processing arithmetic device includes a second processor configured to:
input the feature data;
store the feature data in a first memory; and
store, in the first memory, recognition result data based on a result of execution of recognition processing for the feature data,
the first post-processing arithmetic device is further coupled to a second preprocessing arithmetic device and a third preprocessing arithmetic device,
the first preprocessing arithmetic device, the second preprocessing arithmetic device and the third preprocessing arithmetic device operate in parallel with one another, and
the first post-processing arithmetic device executes the recognition processing based on a reception of completion notifications from all of the first preprocessing arithmetic device, the second preprocessing arithmetic device and the third preprocessing arithmetic device,
the second preprocessing arithmetic device includes a third processor and is configured to execute preprocessing for second analog data from a second sensor which is a sound sensor, the third processor is configured to:
receive analog sound data from the sound sensor and converts the analog sound data into digital sound data; and
output sound feature data based on a result of execution of the feature extraction processing for the digital sound data, and
the second processor is configured to:
input the sound feature data;
store the sound feature data in the first memory; and
store sound recognition result data in the first memory based on a result of execution of the recognition processing for the sound feature data.