CPC G06F 13/1689 (2013.01) | 20 Claims |
1. A memory device, comprising:
an array of memory cells organized into at least one bank;
a write data register to temporarily store write data associated with a write operation directed to the at least one bank;
a timer register to store a timer value associated with the temporarily stored write data, the timer value representing a predefined write time interval; and
circuitry to selectively provide information relating to the write operation upon expiration of the timer value.
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