US 11,755,508 B2
High-performance, high-capacity memory systems and modules
Frederick A. Ware, Los Altos Hills, CA (US); Ely Tsern, Los Altos, CA (US); John Eric Linstadt, Palo Alto, CA (US); Thomas J. Giovannini, San Jose, CA (US); Craig E. Hampel, Los Altos, CA (US); Scott C. Best, Palo Alto, CA (US); and John Yan, San Jose, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Oct. 21, 2021, as Appl. No. 17/507,588.
Application 17/507,588 is a division of application No. 15/525,379, abandoned, previously published as PCT/US2015/060057, filed on Nov. 11, 2015.
Claims priority of provisional application 62/203,279, filed on Aug. 10, 2015.
Claims priority of provisional application 62/085,802, filed on Dec. 1, 2014.
Prior Publication US 2022/0043762 A1, Feb. 10, 2022
Int. Cl. G06F 13/16 (2006.01)
CPC G06F 13/1678 (2013.01) [G06F 13/1673 (2013.01); G06F 13/1694 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A motherboard comprising:
a memory-controller component;
a first memory-module socket adjacent the memory-controller component;
a second memory-module socket adjacent the first memory-module socket on a side of the first memory-module socket opposite the memory-controller component;
a third memory-module socket adjacent the second memory-module socket on a side of the second memory-module socket opposite the first memory-module socket;
a fourth memory-module socket adjacent the third memory-module socket on a side of the third memory-module socket opposite the second memory-module socket;
a first data-link group coupling the memory-controller component to the first memory module socket and the third memory-module socket, the first data-link group extending past the second memory-module socket;
a second data-link group extending past the first memory-module socket and the third memory-module socket, the second data-link group coupling the memory-controller component to the second memory module socket and the fourth memory-module socket;
a third data-link group extending between the first memory-module socket and the second memory-module socket; and
a fourth data-link group extending between the third memory-module socket and the fourth memory-module socket.