US 11,755,249 B2
Storage system including storage nodes to determine cache allocations to implement cache control
Masahiro Tsuruya, Tokyo (JP); Tomohiro Yoshihara, Tokyo (JP); Ryosuke Tatsumi, Tokyo (JP); and Shinsuke Izawa, Tokyo (JP)
Assigned to HITACHI, LTD., Tokyo (JP)
Filed by Hitachi, Ltd., Tokyo (JP)
Filed on Apr. 28, 2022, as Appl. No. 17/731,626.
Application 17/731,626 is a continuation of application No. 16/551,778, filed on Aug. 27, 2019, granted, now 11,347,432.
Claims priority of application No. 2019-033920 (JP), filed on Feb. 27, 2019.
Prior Publication US 2022/0253250 A1, Aug. 11, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 12/0895 (2016.01)
CPC G06F 3/0659 (2013.01) [G06F 3/067 (2013.01); G06F 3/0613 (2013.01); G06F 3/0656 (2013.01); G06F 12/0895 (2013.01); G06F 2212/305 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A storage system, comprising:
a plurality of storage nodes that communicate via a network,
wherein each of the plurality of storage nodes includes one or more controllers and is connected with storage devices for storing data,
wherein at least one controller of the controllers specifies at least two controllers that allocate a cache sub-area where write data is stored based on a controller that receives the write data from a host and a controller that processes the write data,
wherein the cache sub-area is allocated in the specified controllers,
wherein in a case where the controller that processes the write data refers to data stored in a storage device for processing the write data, the controller that processes the write data is included in the at least two controllers,
wherein, in a case where an access pattern of a write request from the host is sequential, the at least one controller specifies the at least two controllers based on a condition that the controller that processes the write data refers to the data stored in the storage device for processing the write data, and
wherein, in a case where an access pattern of the write request from the host is random, the at least one controller specifies the at least two controllers based on a cache utilization efficiency.