US 11,755,216 B2
Cache memory architecture and management
Michael Scharland, Franklin, MA (US); Mark Halstead, Holliston, MA (US); Rong Yu, West Roxbury, MA (US); Peng Wu, Westborough, MA (US); and Benjamin Yoder, Chandler, AZ (US)
Assigned to EMC IP Holding Company LLC, Hopkinton, MA (US)
Filed by Dell Products L.P., Round Rock, TX (US)
Filed on Jan. 28, 2022, as Appl. No. 17/586,901.
Application 17/586,901 is a continuation in part of application No. 17/385,257, filed on Jul. 26, 2021, granted, now 11,599,461.
Prior Publication US 2023/0021424 A1, Jan. 26, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/0831 (2016.01)
CPC G06F 3/0635 (2013.01) [G06F 3/0613 (2013.01); G06F 3/0659 (2013.01); G06F 3/0683 (2013.01); G06F 12/0246 (2013.01); G06F 12/0833 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
establishing a logical block address (LBA) bucket with at least one LBA group; and
associating the at least one LBA group with two or more distinctly sized cache slots based on an input/output (IO) workload received by a storage array, wherein the association includes:
binding the two or more distinctly sized cache slots with the at least one LBA group, and
mapping the bound distinctly sized cache slots in a searchable data structure, wherein the searchable data structure identifies relationships between slot pointers and key metadata.