CPC G06F 3/0629 (2013.01) [G06F 3/0614 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0207 (2013.01); G06F 12/0882 (2013.01)] | 20 Claims |
1. A data storage device, comprising:
a NAND memory including:
a plurality of dies that each include a plurality of planes, and
a read/write circuit configured to:
determine initial physical column addresses for each of the plurality of planes in each of the plurality of dies, and
store the initial physical column addresses in the NAND memory; and
a controller coupled to the NAND memory and configured to:
send a first cache read command to the NAND memory, wherein the first cache read command indicating that a three-byte address will follow,
send the three-byte address to the NAND memory, wherein the three-byte address including at least a first die address, a first plane address, and a first page address, and
send a second cache read command to the NAND memory,
wherein the read/write circuit is further configured to:
retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the second cache read command from the controller, wherein the first initial physical column address is associated with the first die address and the first plane address,
retrieve a first page of data stored at the first initial physical column address, wherein the first page of data is associated with the first page address, and
output the first page of data to the controller.
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