US 11,755,099 B2
Dynamic core selection for heterogeneous multi-core systems
Youfeng Wu, Palo Alto, CA (US); Shiliang Hu, Los Altos, CA (US); Edson Borin, San Jose, CA (US); and Cheng Wang, San Ramon, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 28, 2022, as Appl. No. 17/852,066.
Application 17/852,066 is a continuation of application No. 16/508,916, filed on Jul. 11, 2019, abandoned.
Application 16/508,916 is a continuation of application No. 14/986,678, filed on Jan. 2, 2016, granted, now 10,437,319, issued on Oct. 8, 2019.
Application 14/986,678 is a continuation of application No. 14/169,955, filed on Jan. 31, 2014, granted, now 9,501,135, issued on Nov. 22, 2016.
Application 14/169,955 is a continuation of application No. 13/046,031, filed on Mar. 11, 2011, granted, now 8,683,243, issued on Mar. 25, 2014.
Prior Publication US 2022/0326756 A1, Oct. 13, 2022
Int. Cl. G06F 1/32 (2019.01); G06F 1/329 (2019.01); G06F 1/3287 (2019.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); G06F 11/34 (2006.01); G06F 9/445 (2018.01); G06F 9/48 (2006.01)
CPC G06F 1/329 (2013.01) [G06F 1/3287 (2013.01); G06F 9/3851 (2013.01); G06F 9/445 (2013.01); G06F 9/4893 (2013.01); G06F 9/5027 (2013.01); G06F 9/5094 (2013.01); G06F 11/3466 (2013.01); G06F 11/3409 (2013.01); G06F 11/3452 (2013.01); G06F 2201/81 (2013.01); G06F 2201/865 (2013.01); G06F 2201/88 (2013.01); G06F 2209/501 (2013.01); Y02D 10/00 (2018.01); Y02D 30/50 (2020.08)] 20 Claims
OG exemplary drawing
 
1. A multi-core computer system comprising:
a first processor core of a first type;
a second processor core of a second type different from the first type; and
software to:
access a user-supplied hint indicative of a user preference to execute program code on the first processor core, the user-supplied hint including a user-defined attribute of the program code;
monitor performance of the program code on the first processor core;
determine, based on the user-defined attribute of the program code, a predicted performance of the program code on the second processor core is better than the performance of the program code on the first processor core; and
ignore the user preference by migrating the program code from the first processor core for execution on the second processor core.