| CPC G06F 1/3237 (2013.01) [G06F 30/327 (2020.01); G06F 30/396 (2020.01); G06F 2119/06 (2020.01)] | 7 Claims |
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1. A method for modeling power consumption for an integrated circuit, performed by a power consumption modeling system including a processor based on a computer program including at least one instruction, the method comprising:
determining, by the processor, a hierarchy structure regarding a gating level according to a clock flow of a plurality of clock gating cells included in the integrated circuit;
determining, by the processor, a first clock gating domain corresponding to a first clock gating cell and a second clock gating domain corresponding to a second clock gating cell located in a lower level of the hierarchy of the first clock gating cell based on the hierarchy structure;
receiving, by the processor, a first clock gating enable signal applied to the first clock gating cell;
calculating, by the processor, power consumption of the second clock gating domain based on a first logic level of the first clock gating enable signal;
modeling, by the processor, power consumption of the integrated circuit based on the power consumption of the second clock gating domain;
generating, by the processor, a power consumption modeling circuit using the modeled power consumption of the integrated circuit;
implementing, by the processor, the power consumption modeling circuit into hardware implementation; and
using, by the processor, the power consumption modeling circuit to optimize the power consumption of the integrated circuit,
wherein the calculating power consumption of the second clock gating domain comprises:
determining, by the processor, whether a memory is included in a third clock gating domain corresponding to a third clock gating cell;
determining, by the processor, a third weight corresponding to the third clock gating domain based on the operating state of the memory if the memory is included in the third clock gating domain; and
calculating, by the processor, power consumption for the third clock gating domain based on the third weight and a third logic level of a third clock gating enable signal applied to the third clock gating cell,
wherein the determining the third weight corresponding to the third clock gating domain comprises:
obtaining, by the processor, information of at least one signal applied to the memory; and
determining, by the processor, the third weight corresponding to the at least one signal based on a weight look up table,
wherein the third clock gating domain includes a first memory and a second memory,
and wherein the calculating power consumption for the third clock gating domain comprises:
obtaining, by the processor, a first sub-weight from the weight look up table based on a combination of first signals applied to the first memory in a first clock cycle;
obtaining, by the processor, a second sub-weight from the weight look up table based on a combination of second signals applied to the second memory in the first clock cycle;
calculating, by the processor, the third weight corresponding to the third clock gating domain of the first clock cycle by summing the first sub-weight and the second sub-weight;
calculating, by the processor, power consumption corresponding to the third clock gating domain of the first clock cycle based on the third weight;
obtaining, by the processor, a third sub-weight from the weight look up table based on a combination of third signals applied to the first memory in a second clock cycle;
obtaining, by the processor, a fourth sub-weight from the weight look up table based on a combination of fourth signals applied to the second memory in the second clock cycle;
calculating, by the processor, a fourth weight corresponding to the third clock gating domain of the second clock cycle by summing the third sub-weight and the fourth sub-weight; and
calculating, by the processor, power consumption corresponding to the third clock gating domain of the second clock cycle based on the fourth weight.
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