US 11,754,780 B2
Semiconductor package and manufacturing method thereof
Chung-Ming Weng, Hsinchu (TW); Hua-Kuei Lin, Hsinchu (TW); Chen-Hua Yu, Hsinchu (TW); Chung-Shi Liu, Hsinchu (TW); Hao-Yi Tsai, Hsinchu (TW); Cheng-Chieh Hsieh, Tainan (TW); Hung-Yi Kuo, Taipei (TW); Tsung-Yuan Yu, Taipei (TW); Che-Hsiang Hsu, Hsinchu (TW); Chewn-Pu Jou, Hsinchu (TW); and Cheng-Tse Tang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 13, 2021, as Appl. No. 17/319,102.
Prior Publication US 2022/0365273 A1, Nov. 17, 2022
Int. Cl. G02B 6/12 (2006.01); G02B 6/42 (2006.01)
CPC G02B 6/12 (2013.01) [G02B 6/4201 (2013.01); G02B 2006/12061 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a substrate;
a first waveguide disposed on the substrate;
a semiconductor die disposed on the substrate and comprising a second waveguide aligned with the first waveguide; and
an adhesive layer disposed between the first waveguide and the second waveguide, wherein the first waveguide comprises a first bottom dielectric layer, a first polymer waveguide, and a first top dielectric layer sequentially stacked on the substrate, and the adhesive layer is in contact with at least one of the first bottom dielectric layer, the first polymer waveguide, and the first top dielectric layer.