| CPC G01T 1/20184 (2020.05) | 3 Claims |
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1. A nuclear signal inversion method of a nuclear detection simulation device based on a nanosecond light source, comprising
an upper computer, a ZYNQ SoC processor, a synchronous clock, a double data rate type 3 (DDR3), a secure digital (SD) card TF-CARD, a liquid crystal display (LCD) screen, and an output channel for a simulated nuclear pulse signal, wherein the upper computer is connected to the ZYNQ SoC processor through a 1000 M Ethernet, a USB3.0, and a RS232 respectively; and
the synchronous clock, the DDR3, and the SD card are respectively connected to the ZYNQ SoC processor, and the ZYNQ SoC processor is connected to the output channel for the simulated nuclear pulse signal;
the ZYNQ SoC processor comprises a field programmable gate array (FPGA) unit and an advanced RISC machine (ARM) unit, and the FPGA unit is connected to the ARM unit through an AXI bus;
the LCD screen is directly connected to the FPGA unit of the ZYNQ SoC processor through an IO port;
the SD card is connected to the ARM unit of the ZYNQ SoC processor;
the synchronous clock is connected to the FPGA unit and the ARM unit of the ZYNQ SoC processor synchronously to provide the synchronous clock for the FPGA unit and the ARM unit;
the output channel for the simulated nuclear pulse signal comprises a DAC, a current amplifier, an LED, an optical filter, a photomultiplier tube (PMT), and a high-voltage divider tube seat;
the DDR3 is connected to the ARM unit of the ZYNQ;
an input pin of the DAC is connected in parallel to the FPGA unit of the ZYNQ through an IO port;
the current amplifier is connected to an output pin of the DAC;
the LED is connected to an output pin of the current amplifier;
the LED is closely attached to the optical filter;
the optical filter is directly attached to a light-receiving surface of the PMT; and
the PMT is connected to a preamplifier; and
the nuclear detection simulation device further comprises a power supply, wherein the power supply is respectively connected to the upper computer, the ZYNQ SoC processor, the synchronous clock, the DDR3, the SD card, the LCD screen, and the output channel for the simulated nuclear pulse signal; and
method comprises the following steps:
(1) setting, by an upper computer, corresponding parameters according to user-selected functions, then generating an energy spectrum curve with a corresponding statistical fluctuation phenomenon using Monte Carlo simulation and a large amount of real data according to the parameters, and performing animated demonstration of a detection process of a scintillator detector and a spectrometer to a radioactive source;
(2) sending, by the upper computer, a spectral line and the set parameters to a ZYNQ SoC processor, or pre-storing the spectral line in a SD card;
(3) inverting, by an ARM unit of the ZYNQ SoC processor, the spectral line into amplitude information of a series of random nuclear pulse signals; or when simulation of the radioactive source is selected, directly generating, by the ZYNQ SoC processor, amplitude information of a series of random nuclear pulse conforming to characteristics of the radioactive source;
(4) determining, by the ARM unit of the ZYNQ SoC processor, whether fast components and slow components are contained, and whether the self-radiation and the electron pair effect are generated according to a type of a scintillator, and generating a series of random nuclear pulse signal sequence data containing different rise times, fall times, and amplitudes according to a calculated proportional relationship of the contained fast components and slow components and self-radiated nuclear pulse signals combined with the amplitude information of the random nuclear pulse;
(5) sending, by the ARM unit of the ZYNQ SoC processor, data to an FPGA unit;
(6) generating, by the FPGA unit, a uniform random number according to the data, and then generating an exponentially distributed random number according to the uniform random number as an output time interval of each nuclear pulse signal;
(7) adjusting the output time interval according to scintillation efficiency and detection efficiency of the scintillator detector;
(8) since the FPGA unit is equipped with a counter, when a value of the counter is equal to the time interval, outputting nuclear pulse digital signals sequentially according to a nuclear pulse signal sequence, and when the time interval is less than a pulse width of the nuclear pulse signals, outputting piled-up nuclear pulse signals, wherein up to tenfold pileup is capable of being achieved; and
(9) converting the nuclear pulse digital signals into simulated nuclear pulse signals through a DAC, then amplifying the simulated nuclear pulse signals through a current amplifier to drive an LED to output nuclear pulse optical signals, illuminating a PMT by the optical signals after attenuation by an optical filter, converting the optical signals into electrical signals by the PMT, and then outputting the electrical signals from an anode.
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