US 11,754,621 B2
Method and device for wafer-level testing
Jun He, Hsinchu (TW); Yu-Ting Lin, Hsin-Chu (TW); Wei-Hsun Lin, Hsinchu County (TW); Yung-Liang Kuo, Hsinchu (TW); and Yinlung Lu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jun. 29, 2022, as Appl. No. 17/809,577.
Application 17/809,577 is a continuation of application No. 17/198,764, filed on Mar. 11, 2021, granted, now 11,448,692.
Application 17/198,764 is a continuation in part of application No. 16/522,551, filed on Jul. 25, 2019, granted, now 11,073,551, issued on Jul. 21, 2021.
Claims priority of provisional application 63/115,280, filed on Nov. 18, 2020.
Claims priority of provisional application 63/092,743, filed on Oct. 16, 2020.
Claims priority of provisional application 62/719,044, filed on Aug. 16, 2018.
Prior Publication US 2022/0326300 A1, Oct. 13, 2022
Int. Cl. G01R 31/28 (2006.01); G01R 31/26 (2020.01)
CPC G01R 31/2879 (2013.01) [G01R 31/2642 (2013.01); G01R 31/2886 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
applying a voltage having a first voltage level to an input terminal of a device under test (DUT) during a first period;
applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period, the stress signal including a first sequence and a second sequence, the first sequence having a first ramp-up stage and a first ramp-down stage, and the second sequence having a second ramp-up stage and a second ramp-down stage, wherein the stress signal ramps to a second voltage level during the first ramp-up stage and ramps down to a third voltage level during the first ramp-down stage, and wherein the stress signal ramps to the second voltage level during the second ramp-up stage and ramps down to ground during the second ramp-down stage, wherein the second voltage level and the third voltage level are both different from the first voltage level, wherein the second voltage level is greater than the third voltage level;
obtaining an output signal in response to the stress signal at an output terminal of the DUT; and
comparing the output signal with the stress signal.