| US 7,590,965 B1 | ||
| Methods of generating a design architecture tailored to specified requirements of a PLD design | ||
| Michael George Ingoldby, Boulder, Colo. (US); James E. Ogden, San Jose, Calif. (US); Jeffrey C. Ward, Thornton, Colo. (US); Stacey Secatch, Longmont, Colo. (US); Restu I. Ismail, San Francisco, Calif. (US); and Thomas E. Fischaber, Golden, Colo. (US) | ||
| Assigned to Xilinx, Inc., San Jose, Calif. (US) | ||
| Filed on Dec. 19, 2006, as Appl. No. 11/642,179. | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—18 [716/16; 716/17] | 20 Claims |
| 1. A computer-implemented method of compiling a hardware description language (HDL) description of a programmable logic device
(PLD) design, the method comprising:
identifying in the HDL description at least one parameter value for the PLD design;
passing the at least one parameter value to a high-level language (HLL) function;
using the HLL function to determine a tailored design architecture based on the at least one parameter value;
returning from the HLL function data specifying the tailored design architecture;
generating an implementation of the PLD design based on the HDL description and the data from the HLL function; and
outputting the implementation of the PLD design,
wherein the identifying, passing, using, returning, generating, and outputting are performed by a computer.
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