| US 7,590,956 B1 | ||
| Methods of detecting unwanted logic in an operational circuit design | ||
| Stephen M. Trimberger, San Jose, Calif. (US) | ||
| Assigned to Xilinx, Inc., San Jose, Calif. (US) | ||
| Filed on Jun. 13, 2007, as Appl. No. 11/818,007. | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—5 | 20 Claims |
| 1. A method of detecting unwanted logic in a circuit design, the method comprising:
inserting a plurality of oscillator circuits into the circuit design;
determining an operating frequency of each oscillator circuit and determining therefrom an expected pattern of relationships
among the operating frequencies;
including in the circuit design a means for monitoring relative operating frequencies of the oscillator circuits relative
to the expected pattern of relationships;
implementing the circuit design in an integrated circuit;
monitoring the relative operating frequencies among the oscillator circuits during operation of the circuit design implemented
in the integrated circuit;
detecting, as a result of the monitoring, a variation between the relative operating frequencies and the expected pattern
of relationships; and
outputting, in response to the detecting, an indicator indicating a presence of the unwanted logic.
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