| US 7,590,952 B2 | ||
| Compact chip package macromodels for chip-package simulation | ||
| Michael W. Beattie, Muenchberg (Germany); Kevin Beattie, legal representative; Byron L. Krauter, Round Rock, Tex. (US); and Hui Zheng, Round Rock, Tex. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Nov. 28, 2006, as Appl. No. 11/563,704. | ||
| Prior Publication US 2008/0127010 A1, May 29, 2008 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—1 | 20 Claims |
| 1. A computer implemented method for reducing a chip package model, the computer implemented method comprising:
responsive to receiving the chip package model, creating an inductor model of the chip package model and a resistor model
of the chip package model, using a computer;
measuring a plurality of inductance node voltages of the inductor model of the chip package model, wherein the inductance
node voltages are measured using only a set of external nodes of the inductor model of the chip package model, and wherein
the measured inductance node voltages are used to form a reduced node inductance matrix;
measuring a plurality of resistance node voltages of the resistor model of the chip package model, wherein the resistance
node voltages are measured using only the set of external nodes of the resistor model of the chip package model, and wherein
the measured resistance node voltages are used to form a reduced node resistance matrix;
creating a reduced node inductor model and a reduced node resistor model from the inductance matrix and the resistance matrix,
respectively; and
combining the reduced node resistor model and the reduced node inductor model to form a combined reduced node resistor-inductor
chip package model.
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