| US 7,590,929 B2 | ||
| Record reproduction method, apparatus, and circuit for using error correcting code | ||
| Toshihiko Morita, Kawasaki (Japan); Mitsuhiko Ohta, Kanagawa (Japan); and Takao Sugawara, Isehara (Japan) | ||
| Assigned to Fujitsu Limited, Kawasaki (Japan) | ||
| Filed on Jun. 16, 2004, as Appl. No. 10/869,585. | ||
| Claims priority of application No. 2003-329071 (JP), filed on Sep. 19, 2003. | ||
| Prior Publication US 2005/0066261 A1, Mar. 24, 2005 | ||
| Int. Cl. H03M 13/00 (2006.01) | ||
| U.S. Cl. 714—800 [714/755; 714/758; 714/794; 714/795; 341/59] | 11 Claims |
| 1. A record reproduction apparatus that uses an error correcting code and an iterative method, comprising:
an encoding unit that divides sector data to be written into a recording medium into plural blocks and encodes each of the
blocks using an LDPC code;
an iterative decoding unit that divides data read from the recording medium into the plural blocks and iteratively decodes
each of the blocks divided from the read data using an LDPC decoder; and
an error correcting unit that corrects, after the iterative decoding unit iteratively decodes the sector data, an error based
on a predetermined length of parity symbols, the predetermined length of parity symbols being equivalent to two times as many
as a number of correctable symbol errors, wherein
the predetermined length of parity symbols is determined so that a total error correction capability with the LDPC code is
equal or more than a total error correction capability in the case that the sector data is not divided before encoded using
the LDPC code.
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