| US 7,590,920 B2 | ||
| Reduced complexity error correction encoding techniques | ||
| Shaohua Yang, San Jose, Calif. (US); Mario Blaum, San Jose, Calif. (US); Richard Leo Galbraith, Rochester, Minn. (US); Ksenija Lakovic, San Jose, Calif. (US); Yuan Xing Lee, San Jose, Calif. (US); Travis Oenning, Rochester, Minn. (US); Jongseung Park, Rochester, Minn. (US); and Hideki Sawaguchi, Sunnyvale, Calif. (US) | ||
| Assigned to Hitachi Global Storage Technologies Netherlands, B.V., Amsterdam (Netherlands) | ||
| Filed on Aug. 05, 2005, as Appl. No. 11/198,943. | ||
| Prior Publication US 2007/0043997 A1, Feb. 22, 2007 | ||
| Int. Cl. H03M 13/00 (2006.01) | ||
| U.S. Cl. 714—774 [714/779] | 10 Claims |
| 1. A data storage apparatus for recording data on a storage medium, the data storage apparatus comprising:
means for encoding input bits using a first error correction code to generate first redundant bits that are combined with
the input bits to generate a codeword, wherein dummy bits are located among bits in the codeword;
means for encoding segments of bits in the codeword using a first component code of an error correction composite code to
generate first intermediate values;
means for encoding segments of bits in the codeword that do not contain one of the dummy bits using a second component code
of the error correction composite code to generate second intermediate values;
means for applying a logic function to the first and the second intermediate values to generate second redundant bits of the
error correction composite code; and
means for inserting the second redundant bits into the codeword to replace the dummy bits.
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