a coprocessor having a subset of floating-point instructions instantiated in configurable logic of an IC responsive at least in part to a core configuration bitstream for the coprocessor, the configurable logic including configurable logic blocks of the IC;

a processor coupled to the coprocessor via control circuitry, the control circuitry being external to the coprocessor and being internal to the IC, the processor being internal to the IC;

the control circuitry coupled to a pipeline of the processor and configured for lock-step operation with the pipeline of the processor at a rated speed of the processor;

the control circuitry including monitoring logic for monitoring the pipeline of the processor, the monitoring logic coupled to receive execute signals from an execution stage of the processor for tracking execute states of an instruction progressing through a portion of the pipeline of the processor;

the processor coupled for receiving each instruction of a set of instructions for both the processor and the coprocessor, a portion of the set of instructions being for the coprocessor, the portion being sent to the coprocessor after having been received by the processor;

a control register, wherein responsive to a floating-point instruction sent from the processor to the control circuitry, the control circuitry queries the control register to determine whether the floating-point instruction is part of a set of disabled floating-point instructions; and

means for indicating to the processor that the floating-point instruction is not executable by the coprocessor.