a state machine external to a processor, the processor having the processor pipeline, the state machine being for the tracking of the instruction through the processor pipeline, the state machine having registers for storing a plurality of states, the plurality of states including:

a decode state associated with a decode stage of the processor pipeline;

execution states associated with an execution stage of the processor pipeline, the execution states divided according to at least one of clock cycle of an operation and type of the operation;

a write back state associated with a write back stage of the processor pipeline; and

a load write back state associated with a load write back stage of the processor pipeline;

wherein an initial execution state of the execution states is associated with a first clock cycle of the operation;

the auxiliary processing unit controller configured to generate a write back signal;

the write back signal generated by the auxiliary processing unit controller responsive to location of the instruction within the processor pipeline; and

the write back signal for providing to an auxiliary processing unit coupled to the auxiliary processing unit controller, the write back signal providing an indication that registers of the auxiliary processing unit are capable of being updated.